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datasheet 14-bit configurable registered buffer for ddr2 icssstuaf32869a 14-bit configurable registered buffer for ddr2 1 icssstuaf32869a 7095/13 description the icssstuaf32869a is 14-bit 1:2 registered buffer with parity, designed for 1.7 v to 1.9 v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8v cmos drivers optimized to drive the ddr2 dimm load. they provide 50% more dynamic driver strength than the standard sstu32864 outputs. the icssstuaf32869a operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high, and clk going low. the device supports low-power standby operation. when the reset input (reset ) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs except ptyerr are forced low. the lvcmos reset input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 rdimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the out puts will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, th e register will become active quickly, relative to the time to enable the differential input receivers. icssstuaf32869a must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of reset and the input receivers are fully enabled. this will ensures that there are no g litches on the output. the device monitors both dcs and csr inputs and will gate the qn, ppo (paritial-parity-out) and ptyerr (parity error) parity outputs from changing states when both dcs and csr are high. if either dcs and csr input is low, the qn, ppo and ptyerr outputs will function normally. the reset input has priority over the dcs and csr controls and will force the qn and ppo outputs low and the ptyerr high. the icssstuaf32869a includ es a parity checking function. the icssstua f32869a accepts a parity bit from the memory controller at its input pin parin one or two cycles after the corresponding data input, compares it with the data received on the d-inputs and indicates on its opendrain ptyerr pin (active low) whether a parity error has occurred. the number of cycles depends on the setting of c1. when used as a single device, the c1 input is tied low. when used in pairs, the c1 inpu ts is tied low for the first register (front) and the c1 input is tied high for the second register. when used as a single register, the ppo and ptyerr signals are produced two clock cycles after the corresponding data input. when used in pairs, the ptyerr signals of the first register are left floating. the ppo outputs of the first register are cascaded to the parin signas on the second register (back). the ppo and ptyerr signals of the second register are produced three clock cycles after the corresponding data input. parity implimentation and device wiring for single and dual die is described in the diagram below. if an error occurs, and the ptyerr is driven low, it stays low for two clock cycles or until reset is driven low. the dimm-dependent signals (dcke, dcs, csr and dodt) are not included in the parity check computations. all registers used on an individual dimm must be of the same configuration, i.e single or dual die. features ? 14-bit 1:2 registered buffer with parity check functionality ? supports sstl_18 jedec specification on data inputs and outputs ? 50% more dynamic driver strength than standard sstu32864 ? supports lvcmos switching levels on c1 and reset inputs ? low voltage operation: v dd = 1.7v to 1.9v ? available in 150 bga package applications ? ddr2 memory modules ? provides complete d dr dimm solution with ics98ulpa877a or idtcspua877a ? ideal for ddr2 400, 533, and 667
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 2 icssstuaf32869a 7095/13 parity implementation and device wiring block diagram note: 1.this range does not include d1, d4, and d7, and their corresponding outputs. register 1 (front) register 2 (back) parin parin, w4 nc, a8 ppo, w8 nc, a4 ptyerr, w1 nc, a11 ppo, w4 nc, a8 set c=0 for register 1, and c=1 for register 2 ppo reset clk clk dodt qodt a qodt b qcke a qcke b r d q r d q dcke ptyerr r d q q14 a q14 b q1 a q1 b r d q r d q v ref parity generator and checker qcs a qcs b r d q parin d1 d14 dcs0 11 2 2 2 csr (cs active) 2 2 (1) (1) (1)
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 3 icssstuaf32869a 7095/13 block diagram note: 1.parin is used to generate ppo and ptyerr . reset clk clk d2 - d3, d5 - d6, d8 - d14 v ref ce d clk r ce parity check 11 0 1 d clk r d clk r 2 2 ppo ptyerr parin 2 clk r 2-bit counter d clk r 0 1 c1, c2 ce 11 d2 - d3, d5 - d6, d8 - d25 lps0 (internal node) 11 q2 a- q3a, q5a - q6a, q8a - q14a d2 - d3, d5 - d6, d8 - d14 11 ce d clk r ce 11 q2b - q3b, q5b - q6b, q8b - q14b
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 4 icssstuaf32869a 7095/13 pin configuration 150-ball bga top view note: 1.nc denotes a no-connect (ball present but not connected to the die). nb indicates no ball is populated at that gridpoint. a b c d e f v dd gnd v ref v dd v dd gnd nb qckea q2a v dd nb nb v dd gnd gnd nb v dd gnd v dd q3a gnd gnd qodta v dd d3 nc nb v dd v dd nb dcke nb d2 nb qckeb dodt 1 2 3 45 67 89 10 11 g h j k l m v dd d6 csr d5 q5a qcsa v dd nb nc d10 nb nb q6a q8a q9a v dd dcs nb v dd v dd nc gnd gnd d8 nb n p r t v w v dd nb d9 q10a q12a v dd mcl (1) gnd v ref v dd q11a v dd ptyerr nb v dd gnd gnd parin c1 d11 nb gnd gnd gnd q13a v dd nb nc gnd nb gnd nb gnd nb gnd nb v dd u q14a v dd nb gnd nb gnd gnd gnd nb gnd nb gnd gnd nb gnd nb gnd nb d13 nc nb nb nb nb nb nc nb clk nb reset nb clk nc nb nb nc nb nb d14 nc nb nb nc nc nb nb nb nb nb nc nb nb d12 nb gnd gnd ppo gnd gnd nb gnd gnd v dd nb nb gnd gnd gnd gnd nb nb v dd v dd nb v dd v dd v dd v dd v dd v dd nb v dd v dd nb v dd v dd c1 v dd q2b q3b qodtb q5b q6b qcsb v dd q8b q9b q10b q11b q12b q13b q14b v dd nb gnd mcl (1) mcl (1) nc nc nc mcl (1)
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 5 icssstuaf32869a 7095/13 150 ball ctbga pa ckage attributes a b c d e f g h j k l m n p r t u v w 123 4 5 67891011 top view top marking n p r t u v g h j k l m a b c d e f w 1 2 3 4 5 6 7 8 9 10 11 bottom view side view
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 6 icssstuaf32869a 7095/13 function table inputs 1 outputs reset dcs csr clk clk dn, dodt, dcke qn qcs qodt, qcke hll llll hll hhlh hlll or hl or h x q 0 2 q 0 2 q 0 2 hlh llll hlh hhlh hlhl or hl or h x q 0 2 q 0 2 q 0 2 hhl llhl hhl hhhh hhll or hl or h x q 0 2 q 0 2 q 0 2 hhh lq 0 2 hl hhh hq 0 2 hh hhhl or hl or h x q 0 2 q 0 2 q 0 2 lx or floating x or floating x or floating x or floating x or floating l l l 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 output level before the indicated steady-state conditions were established.
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 7 icssstuaf32869a 7095/13 terminal functions signal group terminal name type description ungated inputs dcke, dodt sstl_18 dram function pins not associated with chip select chip select gated inputs d1...d14 1 1 this range does not include d1, d4, and d7, and their corresponding outputs. sstl_18 dram inputs, re-driven only when chip select is low chip select inputs dcs , csr sstl_18 dram chip select signals. these pins initiate dram address/command decodes, and as such at least one will be low when a valid address/command is present. re-driven outputs q1a...q14a 1 , q1b...q14b 1 , qcsn a, b qckena, b qodtna, b sstl_18 outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock parity input parin sstl_18 input parity is received on pin parin, and should maintain odd parity across the d1:d14 inputs, at the rising edge of the clock, one cycle after chip select is low. parity output ppo sstl_18 partial parity output. indicates parity out of d1-d14. parity error output ptyerr open drain when low, this output indicates that a parity error was identified associated with the address and/or command inputs. ptyerr will be active for two clock cycles, and delayed by in total two clock cycles for compatibility with final parity out timing on the industry-standard ddr2 re gister with parity (in jedec definition). configuration inputs c1 sstl_18 when low, the register is configured as register 1. when high, the register is configured as register 2. clock inputs clk, clk sstl_18 differential master clock input pair to the register. the register operation is triggered by a rising edge on the positive clock input (clk). miscellaneous inputs reset sstl_18 input asynchronous reset input. when low, it causes a reset of the internal latches, thereby fo rcing the outp uts low. reset also resets the ptyerr signal. v ref 0.9v nominal input reference voltage for sstl_18 inputs. two pins (internally tied together) are used for increased inputsreliability. v dd power input power supply voltage gnd ground input ground
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 8 icssstuaf32869a 7095/13 parity and standby function table inputs 1 outputs reset dcs csr clk clk of inputs = h (d1 - d14) 2 par in 3 ppo ptyerr 4 hlx even l l h hlx odd l h l hlx even h h l hlx odd h l h hll even l l h hll odd l h l hll even h h l hll odd h l h hhh xxppon 0 ptyerrn 0 h x x l or h l or h x x ppon 0 ptyerrn 0 lx or floating x or floating x or floating x or floating x or floating x or floating l h 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 this range does not include d1, d4, and d7. 3 parin arrives one clock cycle (c1 = 0), or two clock cycles (c1 = 1), after the data to which it applies. 4 this transition assumes ptyerr is high at the crossing of clk going high and clk going low. if ptyerr is low, it stays latched low for two clock cycles or until reset is driven low. parin is used to generate ppo and ptyerr .
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 9 icssstuaf32869a 7095/13 absolute maximum ratings stresses greater than those listed under absolute maximum ratings ma y cause permanen t damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. mode select output buffer characteristics output edge rates over recommended operating free-air temperature range item rating supply voltage, v dd -0.5v to 2.5v input voltage range, v i 1 1 the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. -0.5v to v dd + 2.5v output voltage range, v o 1,2 2 this current will flow only when the output is in the high state level v o > v ddq . -0.5v to v ddq + 0.5v input clamp current, i ik 50ma output clamp current, i ok 50ma continuous output clamp current, i o 50ma continuous current through each v dd or gnd 100ma package thermal impedance ( ja) 3 3 the package thermal impedance is calculated in accordance with jesd 51. 0m/s airflow 40 c/w 1m/s airflow 29 c/w storage temperature -65 to +150 c c1 device mode 0 first device in pair, front 1 second device in pair, back parameter v dd = 1.8v 0.1v units min. max. dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1 difference between dv/dt_ r (rising edge rate ) and dv/dt_f (falling edge rate). 1v/ns
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 10 icssstuaf32869a 7095/13 operating characteristics, t a = 25 c the reset and cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset is low. symbol parameter min. typ. max. units v dd i/o supply voltage 1.7 1.8 1.9 v v ref reference voltage 0.49 * v dd 0.5 * v dd 0.51 * v dd v v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 v dd v v ih ac high-level input voltage dn, parin, dcs , csr , dcken, dodtn v ref + 0.25 v v il ac low-level input voltage v ref - 0.25 v ih dc high-level input voltage v ref + 0.125 v il dc low-level input voltage v ref - 0.125 v ih high-level input voltage reset , c1 0.65 * v ddq v v il low-level input voltage 0.35 * v ddq v icr common mode input range clk, clk 0.675 1.125 v v id differential input voltage 600 mv i oh high-level output current -12 ma i ol low-level output current 12 i errol ptyerr low-level output current 25 ma t a operating free-air temperature 0 +70 c
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 11 icssstuaf32869a 7095/13 dc electrical characterist ics over operating range following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v ddq /v dd = 1.8v 0.1v. symbol parameter test conditions min. typ. max. units v ik i i = -18ma -1.2 v v oh v ddq = 1.7v, i oh = -100 av ddq -0.2 v v ddq = 1.7v, i oh = -12ma 1.2 v ol v ddq = 1.7v, i ol = 100 a0.2 v v ddq = 1.7v, i ol = 12ma 0.5 v errol ptyerr output low voltage i errol = 25ma; v dd = 1.7v 0.5 v i il all inputs v i = v dd or gnd -5 +5 a i dd static standby i o = 0, v dd = 1.9v, reset = gnd 200 a static operating i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = clk = v ih ( ac ) or v il ( ac ) 10 ma i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = v ih ( ac ), clk = v il ( ac ) 120 i ddd dynamic operating (clock only) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle 247 a/clock mhz dynamic operating (per each data input) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. 52 a/clock mhz/ data c in dn, parin, dscn inputs v i = v ref 250mv 2 3 pf clk and clk inputs v icr = 0.9v, v ipp = 600mv 3.5 4.5 reset v i = v dd or gnd 5
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 12 icssstuaf32869a 7095/13 timing requirements over recommend ed operating free-air temperature range switching characteristics over recommended free air operating range (unless otherwise noted) symbol parameter v dd = 1.8v 0.1v units min. max. f clock clock frequency 410 mhz t w pulse duration, clk, clk high or low 1 ns t act 1 1 v ref must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of t act (max) after reset is taken high. differential inputs active time 10 ns t inact 2 2 v ref , data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of t inact (max) after reset is taken low. differential inputs inactive time 15 ns t su setup time dcs before clk , clk , csr high; csr before clk , clk , dcs high 0.7 ns dcs before clk , clk , csr low 0.5 dodt, docke, and data before clk , clk 0.5 par_in before clk , clk 0.5 t h hold time dcs , dodt, dcke, and data after clk , clk 0.5 ns par_in after clk , clk 0.5 symbol parameter v dd = 1.8v 0.1v units min. max. f max max input clock frequency 340 mhz t pdm propagation delay, single -bit switching, clk / clk to qn 1.1 1.9 ns t pdmss propagation delay, simultaneous switching, clk / clk to qn 2 ns t lh low to high propagation delay, clk / clk to ptyerr 0.9 3 ns t hl high to low propagation delay, clk / clk to ptyerr 0.4 2.4 ns t pd propagation delay from clk / clk to ppo 0.3 1.6 ns t phl high to low propagation delay, reset to qn 3ns t plh low to high propagation delay, reset to ptyerr 3ns
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 13 icssstuaf32869a 7095/13 output buffer characteristics output edge rates over recommended operating free-air temperature range parameter v dd = 1.8v 0.1v units min. max. dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1 difference between dv/dt_ r (rising edge rate ) and dv/dt_f (falling edge rate). 1v/ns
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 14 icssstuaf32869a 7095/13 register timing notes: 1.this range does not include d1, d4, and d7, and their corresponding outputs. 2.parin is used to generate ppo and ptyerr . reset dcs csr clk clk d1 - d14 q1 - q14 parin ppo ptyerr n n+1 n+2 n+3 n+4 t su t h t pd clk to q t su t h t pd t pd clk to ppo clk to ptyerr t pd (2) (2) (2) clk to ptyerr (1) (1)
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 15 icssstuaf32869a 7095/13 register timing notes: 1.this range does not include d1, d4, and d7, and their corresponding outputs. 2.parin is used to generate ppo and ptyerr . reset dcs csr clk clk d1 - d14 q1 - q14 ppo (not used) n n+1 n+2 n+3 n+4 t su t h t pd clk to q t su t h t pd t pd clk to ppo t pd parin (2) (2) (2) ptyerr clk to ptyerr clk to ptyerr (1) (1)
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 16 icssstuaf32869a 7095/13 test circuits and waveforms (v dd = 1.8v 0.1v) simulation load circuit voltage and current waveforms inputs active and inactive times voltage waveforms - pulse duration voltage waveforms - setup and hold times production-test load circuit voltage waveforms - propagation delay times voltage waveforms - propagation delay times notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v dd /2 6. v ih = v ref + 250mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600mv. 9. t plh and t phl are the same as t pdm . c l =30pf r l =1k dut out r l= 100 clk inputs t l =50 t l =350ps,50 test point clk clk v dd r l =1k test point test point v dd 0v v dd /2 lvcmos reset input i dd v dd /2 t inact t act 10% 90% v icr v id v icr input t w v ref v ih v il v ref input v icr v id t su t h clk clk z o =50 test point r l =50 dut out clk inputs clk v dd /2 clk z o =50 z o =50 test point test point clk v icr v id t plh t phl output v oh v ol v icr v tt v tt clk v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 17 icssstuaf32869a 7095/13 test circuits and waveforms (v dd = 1.8v 0.1v) load circuit: high-to-l ow slew-rate adjustment voltage waveforms: high-to-low slew-rate adjustment load circuit: low-to-h igh slew-rate adjustment voltage waveforms: low-to-h igh slew-rate adjustment load circuit: error output measurements voltage waveforms: open drain output low-to-high transition time (w ith respect to reset input) voltage waveforms: open drain output high-to-low transition time (with r espect to clock inputs) voltage waveforms: open drain output low-to-high transition time (with r espect to clock inputs) notes: 1. cl includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). c l =10pf r l =50 dut out test point v dd v oh 80% 20% v ol output dv_f dt_f c l =10pf r l =50 dut out test point v ol 20% 80% v oh output dv_r dt_r c l =10pf r l =1k dut out test point v dd v oh v cc output waveform 2 lvcmos reset input t plh v cc /2 0.15v 0v 0v v cc v icr t hl timing inputs v icr v i(pp) output waveform 1 v cc /2 v ol v oh output waveform 2 0.15v 0v v icr t hl timing inputs v icr v i(pp)
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 18 icssstuaf32869a 7095/13 test circuits and waveforms (v dd = 1.8v 0.1v) partial parity out load circuit partial parity out voltage waveform, propagation delay time with respect to clk input v tt = v tt /2 v icr cross point voltage v i ( pp ) = 600mv t plh and t phl are the same as t pd . dut out c l =5pf (1) testpoint r l =1k clk clk v icr v icr v i(pp) t plh t phl v tt v tt output
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 19 icssstuaf32869a 7095/13 package outline and pack age dimensions - bga package dimensions are kept current with jedec publication no. 95 n p r t u v g h j k l m a b c d e f w 1 2 3 4 5 6 7 8 9 10 11 0 . 6 5 e1 6.50 8.00 0.05 b a 0.15(4x) 0.65 c d 1 1 1 . 7 0 1 3 . 0 0 0 . 0 5 b n p r t u v g h j k l m a b c d e f w 1234567891011 e d a1 corner 0.25 ref 0.03 ref // 0.20 c 0.12 c t 1.20 max h=0.27 ~ 0.37 c s e a t i n g p l a n e d= ? 0.38 ~ 0.48(150x) ? 0.08 ? 0.15 m c cab m bottom view top view a1 corner all dimensions in millimeters d 13.00 bsc e 8.00 bsc t min/max 0.90/1.20 e 0.65 bsc d min/max 0.35/0.48 h min/max 0.25/0.37 d1 11.70 bsc e1 6.50 bsc b 0.65 c 0.75 ball grid ref. dims note: ball grid total indicates maximum ball count for package. lesser quantity may be used. horiz 11 vert 19 total 150
icssstuaf32869a 14-bit configurable register ed buffer for ddr2 commercial temperature grade 14-bit configurable registered buffer for ddr2 20 icssstuaf32869a 7095/13 ordering information xxx xx package device type hlf low profile, fine pitch, ball grid array - lead-free 14-bit configurable registered buffer for ddr2 869a 32 double density icssstuaf xx family shipping carrier x t tape and reel
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